Semiconductor integrated circuits (hereinafter suitably referred to as “LSI”) sometimes have such a defect that the delay value of the element exceeds the standard value (so-called delay fault) due to irregularity in manufacturing. Recently, the operation frequency of the synchronous digital circuit in the LSI is getting higher, and there is a tendency that the defect due to small delay fault becomes the cause of the circuit operation failure. In order to prevent such an operation failure, in the synchronous digital circuit, it is desired to execute a test (hereinafter suitably referred to as “delay test”) to ensure that the circuit operates at the operation frequency actually used, for example, before the shipping.
As the technique of this kind, in case of executing the fault simulation of scan method, there is proposed a technique of activating the logic of the paths from the register to the register and testing whether or not each path can operate at the specification frequency (see. Japanese Laid-open Patent Application No. 02-287271). In addition, there is proposed a technique of specifying the path in which the delay fault is not specified, generating the test pattern capable of detecting the delay fault of those paths and confirming whether or not each path is activated (see. Japanese Laid-open Patent Application No. 2004-54329). Further, there is proposed a technique of executing delay fault simulation to the combinational part of the logic circuit by using the initial value and the transition value of each of the external input pins and the flop-flops (see. Japanese Laid-open Patent Application No. 05-72287).
However, in the above-mentioned conventional techniques, it is difficult to effectively detect the delay fault inside the LSI from outside of the LSI by using the input pattern that operates the LSI according to the actual use form.